1. Technical Field
This disclosure generally relates to a semiconductor device and a manufacturing method thereof and more particularly to a semiconductor device and a manufacturing method thereof in which the semiconductor device is provided with a power MOSFET including a semiconductor substrate constituting a drain, a trench formed on a surface of the semiconductor substrate, a gate electrode in the trench, the gate electrode being made of polysilicon and formed via a gate insulating film, a body diffusion layer on a surface side of the semiconductor substrate, the body diffusion layer being positioned adjacently to the trench and formed shallower than the trench, a source diffusion layer on the surface of the semiconductor substrate, the source diffusion layer being positioned adjacently to the trench and the body diffusion layer and formed shallower than the body diffusion layer, a first interlayer insulating film formed on the gate electrode, and a source electrode film made of a metallic material and formed on the semiconductor substrate, the source electrode film being insulated from the gate electrode and electrically connected to the body diffusion layer and the source diffusion layer.
2. Description of the Related Art
Power MOSFETs are used in the field of power electronics involving high current and high voltage. In recent years, there have been increasing demands for low Ron as power management of batteries for mobile communication devices and trench-gate type power MOSFETs have attracted attention.
FIG. 1 is a cross-sectional view showing a cell portion of a conventional power MOSFET.
An N-type epitaxial layer (N−) 3 formed by epitaxial growth is formed on a surface of an N-type single-crystal silicone substrate (N+) 1. The N-type single-crystal silicone substrate 1 and the N-type epitaxial layer 3 constitute a drain. A gate insulating film 7 is formed on an inner wall of a trench 5 formed on a surface of the N-type epitaxial layer 3. A gate electrode 9 made of polysilicon is formed in the trench 5 via the gate insulating film 7.
A P-type body diffusion layer (P−) 11 is formed adjacently to the trench 5 on a surface side of the N-type epitaxial layer 3. An N-type source diffusion layer 13 is formed adjacently to the trench 5 on a surface side of the P-type body diffusion layer 11. A P-type contact diffusion layer (P+) 15 is formed on a surface of the N-type epitaxial layer 3 with a certain distance from the trench 5 and such a depth as to reach the P-type body diffusion layer 11.
A first interlayer insulating film 18 made of a silicon oxide film, for example, is formed on the gate electrode 9. The first interlayer insulating film 18 is formed in a protrusion manner relative to the surface of the N-type epitaxial layer 3 and covers a portion of the N-type source diffusion layer 13 adjacent to the trench 5. A source electrode film 19 is formed on the N-type source diffusion layer 13, the P-type contact diffusion layer 15, and the first interlayer insulating film 18.
Such a power MOSFET is disclosed in Patent Document 1, for example.
In the power MOSFET shown in FIG. 1, the first interlayer insulating film 18 for insulation between the gate electrode 9 and the source electrode film 19 must be patterned by a photoengraving technique and an etching technique, so that it is necessary to have a pattern width larger than a width of the trench 5 taking into consideration a shift of mask positioning upon performing photoengraving. Thus, it is impossible to reduce a mesa width (trench-to-trench distance) to a certain limit or less and miniaturization of the device is hindered.
In view of this, there has been disclosed a structure in which the first interlayer insulating film between the gate electrode and the source electrode film is left only in a width of the trench (refer to Patent Document 2).
FIG. 2 is a cross-sectional view showing a cell portion of other conventional power MOSFET.
As shown in FIG. 2, the first interlayer insulating film 18 is formed only in the trench 5. A top surface of the first interlayer insulating film 18 is formed in a recessed manner relative to the surface of the N-type epitaxial layer 3.
In this structure, even if the mesa width (trench-to-trench distance) is reduced, it is possible to secure a larger contact area in comparison with the case of the structure shown in FIG. 1, the contact area being positioned between the source diffusion layer 13 and the source electrode film 19.
However, this structure poses a problem in that it is difficult to process a film thickness of the first interlayer insulating film 18 in a well-controlled manner. Taking into consideration a change of the film thickness of the first interlayer insulating film 18, it is necessary to have a surface of the gate electrode 9 lower than the surface of the epitaxial layer 3 in accordance with the change of the film thickness. Accordingly, depths of the body diffusion layer 11, the source diffusion layer 13, and the trench 5 are required to be larger, so that longer manufacturing time is necessary and manufacturing of a low volume power MOSFET is hindered.
Moreover, in the conventional techniques shown in FIG. 1 and FIG. 2, unevenness of the surface of the N-type epitaxial layer 3 in the vicinity of the trench 5 is large, coverage of the source electrode film 19 is deteriorated, and failure such as a void 49 is generated in the source electrode film 19 as shown in FIG. 3.
In accordance with this failure, there have been problems in which a flow of current of the source electrode film 19 is hindered and impact upon wirebonding is not absorbed.
Further, when the source electrode film 19 is plated for bump connection, if the coverage of the source electrode film 19 is not good, a thin portion of the source electrode film 19 is damaged upon plating and the N-type source diffusion layer 13 and the P-type body diffusion layer 11 below the source electrode film 19 are also damaged. In accordance with this, failure of a short circuit between the source electrode film 19 and the N-type epitaxial layer 3 is likely to be generated.
Patent Document 1: Japanese Laid-Open Patent Application No. 2002-26324
Patent Document 2: Japanese Laid-Open Patent Application No. 2001-85685
Due to the above-mentioned reasons, preferably, a lower structure of the source electrode film is made flat.